The most common technique for manufacturing integrated circuits today is the planer technology method whereby individual circuits are formed below the surface of a semiconductor substrate (i.e., a wafer). The planer technology method is conventionally practiced by first fabricating an ingot of substantially pure semiconductor material which is then sliced to yield individual wafers. Next, at least one layer of semiconductor material of a different type is formed (i.e., epitaxially grown) on the upper surface of each wafer. Thereafter, the surface of the upper epitaxial layer on each wafer is passivated, and then is selectively etched by photolithographic techniques to create openings in which semiconductor junctions are formed. After formation of the semiconductor junctions, interconnections between the junctions in each wafer are formed by depositing a metal such as aluminum.
Once the individual circuits are formed on each wafer, the circuits are tested by probing using a conventional probe designed for that purpose. Those circuits which are found to be defective during probing are recorded as to their location on the wafer. Following probing, each wafer is then diced into circuit-containing chips, the defect-free ones of which are thereafter each separately packaged to yield individual integrated circuits.
As may be appreciated, the manufacture of integrated circuits by the above-described method is complex and involves many different process steps. Failure to execute one or more process steps correctly on one or more wafers in a batch will likely cause one or more circuits on each wafer to fail, such circuit failures being referred to as defects. Further, random defects (circuit failures) can and do occur. Usually, there is little that can be done to avoid random defects. Often, however, defects are spatially clustered as a result of one or more process steps being improperly executed. A knowledge of which of the process steps was not properly executed can lead to improved performance through process modification.
Presently, there are no known automated techniques which use data on failed circuits and their spatial location on a semiconductor wafer to identify the process steps and/or failure modes (if any) to which such defects are attributable. Rather, defect characterization is typically accomplished by failure mode analysis, which is time consuming and expensive (such failure mode analysis of a single lot can take up to three days).
Therefore, there is need for an automated technique which can characterize sources of defects on a semiconductor wafer.